Algorithmic level low-power VLSI design applied to RGB to HSI conversion

Abstract

The growing demand for portable applications such as cellular phones, portable digital assistants (PDAs) and notebooks has resulted in a requirement for integrated circuits (ICs) which consume less power while delivering the same performance as non-portable appliances. In addition, the low-power implementation of non-portable circuits has several advantages, notably a marketing advantage in terms of energy efficiency and reduced manufacturing costs because of cheaper packaging. The focus of this thesis is the application of high-level low-power VLSI design methods to a hardware implementation of Render's algorithm which converts a camera signal of red, green and blue into a human perception-based code of hue, saturation and intensity. The aim was to consider the circuit implementation of the algorithm on a block-by-block basis in order to identify in each block potential avenues along which power savings can be made, and to produce a power-efficient high-level circuit design targeted to an Application Specific hitegrated Circuit (ASIC). The most commonly used approach for power reduction in VLSI circuits is to minimise the supply voltage. However, with ASICs voltage scaling is only applicable within a very limited range. Therefore, this thesis concentrates on the minimisation of the power consumption by reducing the active capacitance of the circuit. This required a high-level power estimation tool capable of assessing the power consumption at the earliest possible design stage, and therefore led to the development a tool that can rapidly measure the active capacitance of a design from a VHDL netlist.