Effect of the Gate Volume on the Performance of Printed Nanosheet Network-Based Transistors

Abstract

Demonstration of high-performance, all-printed transistors fabricated only from networks of two-dimensional nanosheets would represent a significant advance in printed electronics. However, such devices have only been shown to work via electrolytic gating. Under those circumstances, both channel/electrolyte and gate/electrolyte interfaces show significant capacitances which, when unoptimized, lead to reduced device performance. Here, we fabricate a range of printed thin-film transistors (TFTs) with WSe2 and graphene nanosheet networks acting as the channel and gate electrodes. We find that transistor operation depends sensitively on the ratio of the gate electrode to channel volume such that effective mobility is only maximized when the gate volume is >10 times larger than the channel volume. These results indicate that all-printed, all-nanosheet stacked heterostructure TFTs will require relatively thick gates to operate effectively.