Hardware support for power and area efficient construction of high-quality bounding volume hierarchies

Abstract

Rendering methods basal on ray-tracing hold the promise of great realism for interactive applications. However, these algorithms still involve a considerable computational cost relative to the capabilities of today�۪s hardware. In response to this, a large body of research directed towards improving the elficiency and performance of interactive ray-tracing systems has emerged in recent years. Although modern graphics processors have evolved to support ray-tracing through general-purpose compute capabilities, this approach requires engaging a large amount of hardware resources for optimal performance. Moreover, recent developments, such as the rise of mobile computing, and the emergence of power-efficiency as the primary limit to processor scalability, have placed power near the top of the agenda.