Vectorization for accelerated gather/scatter and multibyte data formats

Abstract

SIMD extensions to the instruction sets of general purpose processors have become widespread, and SIMD width and the capabilities provided by the hardware are steadily increasing with newer processor generations. This thesis tackles two challenges faced by compilers when generating code for modern SIMD extensions: SIMD code generation for interleaved memory access patterns, and SIMD code generation for custom types not provided by hardware. On the topic of SIMD code generation for interleaved memory access, we address strided array access specifically, and propose and evaluate a technique for the generation of SIMD code to gather and scatter data elements between memory and SIMD registers. Our technique extends a prior state of the art technique to support a wider class of interleaved memory access. On the topic of SIMD code generation for custom datatypes, we propose and evaluate a vectorized code generation approach which supports reduced-precision floating point number formats along a continuum between native types. We demonstrate that compilers can generate efficient SIMD code for both challenges using modern SIMD extensions, without requiring special hardware support beyond the general-purpose data movement and reorganization features already present in a variety of modern SIMD-enhanced general purpose processors.