Distributed shared memory architectures and global performance state estimation

Abstract

Invasive and non-invasive methods may be applied to measure and analyse the performance of hardware Distributed Shared Memory (DSM) systems. This thesis presents novel solutions for both methods and discusses the architectural organisation of loosely and tightly coupled systems. The work begins with a discussion of the design and implementation of a non-invasive deep-trace instrument for high-speed interconnects and also deals with the analysis of the trace-data. Analysis results are used to tune interconnect simulations. This thesis then presents an innovative invasive approach to estimate and predict the system-wide utilisation of computational resources in real-time. An algorithm that implements a discrete minimum mean-square error filter is applied to fuse concurrent and sequential observations of system event counts into a state-vector. Contemporary computer components and subsystems make these event counts available through hardware Performance Monitoring Counter (PMC) registers. The registers may be accessed by the system’s software quasi-concurrently but the number of registers in individual components is usually smaller than the number of events that can be monitored. This approach overcomes the problem by modelling individual PMC readings as vector random processes and recursively processes them one PMC set at a time into a common state-vector, thereby making larger PMC sets observable than would otherwise be possible. Finally this work looks at loosely and tightly coupled hardware DSM systems as targets for the estimation algorithm. Particular attention is paid to the conceptual design of a tightly coupled hybrid reconfigurable DSM graphics cluster.