Show simple item record

dc.contributor.authorGREGG, DAVID
dc.date.accessioned2008-04-26T07:06:53Z
dc.date.available2008-04-26T07:06:53Z
dc.date.issued2006
dc.date.submitted2006en
dc.identifier.citationOwen Callanan, David Gregg, Andy Nisbet and Mike Peardon, High performance scientific computing using FPGAs with IEEE floating point and logarithmic arithmetic for Lattice QCD: proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL 06), Madrid, Spain, 2006, pp29 - 34en
dc.identifier.issn42827
dc.identifier.otherY
dc.identifier.otherYen
dc.identifier.urihttp://hdl.handle.net/2262/16482
dc.descriptionPUBLISHEDen
dc.description.abstractThe recent development of large FPGAs along with the availability of a variety of floating point cores have made it possible to implement high-performance matrix and vector kernel operations on FPGAs. In this paper we seek to evaluate the performance of FPGAs for real scientific computations by implementing Lattice QCD, one of the classic scientific computing problems. Lattice QCD is the focus of considerable research work worldwide, including two custom ASIC-based solutions. Our results give significant insights into the usefulness of FPGAs for scientific computing. We also seek to evaluate two different number systems available for running scientific computations on FPGAs. To do this we implement FPGA based lattice QCD processors using both double precision IEEE floating point and single precision equivalent Logarithmic Number System (LNS) cores and compare their performance with that of two lattice QCD targeted ASIC based solutions and with PC cluster based solutions.*en
dc.description.sponsorshipSponsored by the Irish Research Council for Science Engineering & Technology under grant SC/02/288en
dc.format.extent29en
dc.format.extent34en
dc.format.extent200088 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoenen
dc.publisherIEEEen
dc.rightsYen
dc.subjectFPGAsen
dc.subjectLattice QCDen
dc.titleHigh performance scientific computing using FPGAs with IEEE floating point and logarithmic arithmetic for Lattice QCDen
dc.title.alternativeInternational Conference on Field Programmable Logic and Applications (FPL 06): 16th : 2006 : Madriden
dc.typeConference Paperen
dc.type.supercollectionscholarly_publicationsen
dc.type.supercollectionrefereed_publicationsen
dc.identifier.peoplefinderurlhttp://people.tcd.ie/dgregg
dc.identifier.rssinternalid42827
dc.identifier.rssurihttp://ieeexplore.ieee.org/iel5/4095018/4100939/04100953.pdf?tp=&isnumber=4100939&arnumber=4100953
dc.contributor.sponsorIrish Research Council for Science Engineering and Technology


Files in this item

Thumbnail
Thumbnail

This item appears in the following Collection(s)

Show simple item record