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dc.contributor.advisorBoland, John
dc.contributor.authorGLEESON, PETER DECLAN
dc.date.accessioned2019-09-27T11:44:35Z
dc.date.available2019-09-27T11:44:35Z
dc.date.issued2019en
dc.date.submitted2019
dc.identifier.citationGLEESON, PETER DECLAN, Nanoelectromechanical relays for low power integrated circuits, Trinity College Dublin.School of Chemistry, 2019en
dc.identifier.otherYen
dc.identifier.urihttp://hdl.handle.net/2262/89569
dc.descriptionAPPROVEDen
dc.description.abstractThe semiconductor industry roadmap was described by Intel cofounder, Gordon Moore, fifty years ago when he predicted that the number of transistor devices on a silicon integrated circuit would double with every new generation of the technology on a two year cycle. That this exponential growth has been maintained for several decades to the point where a state of the art Si integrated circuit now contains billions of transistors is remarkable, and has transformed the world we live in. The solid state device technologies on which these products have been built now feature dimensions on the order of 10 nm, and this aggressive scaling brings new challenges. With growing demand for data volumes and computing power, much of it mobile, leakage currents and power dissipation are key challenges for the industry. While the progress of the technology to date has been evolutionary, with new materials, device designs and circuit topologies, the fundamental nature of the problems confronting the industry now require revolutionary approaches, with completely new devices and technologies being developed to maintain Moore s law. The future may well look to the past for inspiration in this regard. In the 1930s, computing was carried out using mechanical relay devices by Alan Turing and others. If mechanical devices can be scaled to be compatible with current state of the art integrated circuits, they may well offer solutions to the leakage and power performance issues of state of the art solid state technology. In this work, the challenge of incorporating nano scale relays (nanorelays) to complement or replace solid state devices is explored. The specific challenge of integrating these devices at the 22 nm technology node is explored using validated models and experimental investigation. [1] G. E. Moore, Intel: Memories and the microprocessor, Daedalus, vol. 125, no. 2, pp. 55{80, 1996. [2] C. Teuscher, Alan Turing: Life and legacy of a great thinker. Springer Science & Business Media, 2004.en
dc.language.isoenen
dc.publisherTrinity College Dublin. School of Chemistry. Discipline of Chemistryen
dc.rightsYen
dc.subjectCMOSen
dc.subjectNanorelaysen
dc.subjectEnergy efficiencyen
dc.subjectSubthreshold slopeen
dc.subjectMoore's Lawen
dc.subjectStictionen
dc.titleNanoelectromechanical relays for low power integrated circuitsen
dc.typeThesisen
dc.type.supercollectionthesis_dissertationsen
dc.type.supercollectionrefereed_publicationsen
dc.type.qualificationlevelDoctoralen
dc.identifier.peoplefinderurlhttps://tcdlocalportal.tcd.ie/pls/EnterApex/f?p=800:71:0::::P71_USERNAME:GLEESOPEen
dc.identifier.rssinternalid207218en
dc.rights.ecaccessrightsopenAccess


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