Muiris Woulfe, Eoin Creedon, Ross Brennan, Michael Doyle and Michael Manzke, Programming Models for Reconfigurable Application Accelerators, 1st Workshop on Programming Models for Emerging Architectures (PMEA 2009), Raleigh, North Carolina, USA, 12 September 2009, Marc Gonzalez Tallada, Alejandro Duran Gonzalez, Rosa M Badia Sala and Xavier Martorell Bofill, Barcelona Supercomputing Center, 2009, 77 - 83
Algorithms can be accelerated by offloading computeintensive
operations to application accelerators comprising
reconfigurable hardware devices known as Field Programmable
Gate Arrays (FPGAs). We examine three types
of accelerator programming model – master-worker, message
passing and shared memory – and a typical FPGA
system configuration that utilises each model. We assess
their impact on the partitioning of any given algorithm between
the CPU and the accelerators. The ray tracing algorithm
is subsequently used to review the advantages and
disadvantages of each programming model. We conclude
by comparing their attributes and outlining a set of recommendations
for determining the most appropriate model for
different algorithm types.
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