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dc.contributor.advisorManzke, Michael
dc.contributor.authorCreedon, Eoin
dc.date.accessioned2016-11-07T14:19:55Z
dc.date.available2016-11-07T14:19:55Z
dc.date.issued2010
dc.identifier.citationEoin Creedon, 'FPGA message passing cluster architectures', [thesis], Trinity College (Dublin, Ireland). School of Computer Science & Statistics, 2010, pp 257
dc.identifier.otherTHESIS 8911
dc.identifier.urihttp://hdl.handle.net/2262/77609
dc.description.abstractThis work investigates inter-Field Programmable Gate Array (FPGA) communication mechanisms, specifically the use of message passing and switched Ethernet communication mechanisms. Inter-FPGA communication is required in situations where the computational demands of an algorithm cannot be satisfied by a single FPGA. To meet the algorithms requirements, it must be implemented over several FPGAs. This leads to the need for remote register transfer operations that allow for the exchange of data and synchronisation between aspects of the algorithm that are implemented on each individual FPGAs. The algorithm is de- fined using a Hardware Description Language allowing it to be implemented through the reconfigurable logic of the FPGA. This thesis argues for an implementation of the data exchange and synchronisation mechanisms that facilitate remote register transfer operations in reconfigurable logic on the FPGA. This approach allows for a definition in Hardware Description Language and therefore can provide the application programmer with a Hardware Description Language Application Programming Interface that is simple to integrate into the application and hides the implementation of the communication mechanisms from the application programmer. A message passing protocol is used to implement the remote register transfer operations. Message passing and switched Ethernet are argued for as the approach to be taken as they support algorithm parallelisation in a scalable and robust manner. Using the Hardware Description Language Message Passing Application Programming Interface (HDL MP API) facilitates both the remote register transfer operations between FPGAs and also between FPGAs and workstations. The message passing and switched Ethernet operations can be implemented using either a dedicated hardware microarchitecture or an FPGA processor, with the HDL MP API developed to abstract the application from which data exchange approach is being taken. By looking at both approaches, this thesis argues for the feasibility of message passing in conjunction with switched Ethernet as a viable platform for supporting application parallelisation across interconnected FPGAs. To support this, discussions on characteristics of various parallel algorithms aid in demonstrated which approach is suitable for a given set of algorithm requirements. Using message passing and switched Ethernet, evaluations of both the hardware microarchitecture and an FPGA processor have been undertaken across both 10/100 Mb and Gigabit Ethernet. The evaluations demonstrate the feasibility of using message passing and switched Ethernet as the interconnect structures for distributed FPGAs while also highlighting advantages for implementing the structures in hardware through the lower latency and higher application network bandwidth that is achieved. The hardware microarchitecture is able to achieve a maximum bandwidth of 1800 Mbps while the FPGA processor achieves a maximum bandwidth of 140 Mbps. The HDL MP API has been evaluated for its functionality in supporting parallel algorithms implemented across multiple FPGAs. Parallel Matrix Multiplication has been implemented as a high performance algorithm that can be parallelised across the FPGAs. Experiment results show that the HDL MP API is able to support the algorithms parallel computations across a different number of FPGAs, depending on computational requirements.
dc.format1 volume
dc.language.isoen
dc.publisherTrinity College (Dublin, Ireland). School of Computer Science & Statistics
dc.relation.isversionofhttp://stella.catalogue.tcd.ie/iii/encore/record/C__Rb14374576
dc.subjectComputer Science, Ph.D.
dc.subjectPh.D. Trinity College Dublin
dc.titleFPGA message passing cluster architectures
dc.typethesis
dc.type.supercollectionrefereed_publications
dc.type.supercollectionthesis_dissertations
dc.type.qualificationlevelDoctoral
dc.type.qualificationnameDoctor of Philosophy (Ph.D.)
dc.rights.ecaccessrightsopenAccess
dc.format.extentpaginationpp 257
dc.description.noteTARA (Trinity's Access to Research Archive) has a robust takedown policy. Please contact us if you have any concerns: rssadmin@tcd.ie


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